PMIC Selection

PMICs Matched to the Processor

A power management IC, or PMIC, gathers the several supply rails a processor needs into a single chip, generating and sequencing the core, the I/O, the memory, and the analog rails from one input source. It exists because a modern SoC asks for half a dozen voltages, each at its own level and tolerance, brought up in a fixed order at set times, and building that supply from discrete regulators alone takes board space, a fistful of parts, and a sequencing circuit a PMIC carries on the die. The PMIC trades that part count and that area for a single chip that has to be matched to the processor it serves. The selection turns less on the PMIC’s own specifications than on how well it matches the processor it feeds, since a PMIC is designed around a specific chip or a family of them. A regulator stands on its own numbers, while a PMIC is read mainly on its fit to one processor, and that fit is the thing to check first.

Why the PMIC follows the processor

A processor publishes a power map: a list of rails, each with a voltage, a current, a tolerance, and a place in the start-up order. A PMIC built for that processor carries the right number of rails at the right voltages with the sequencing already designed in, which is the bulk of the work a matched part saves a design. The parts that pair with TI processors, the ones the TI TPS6510 PMICs pair with, are an example of a PMIC family designed against a specific set of SoCs rather than sold as a general regulator.

The strongest case is the NXP i.MX line, where the PMIC choice is part of the processor design. Weighing the NXP PCA9450 and PF8 for an i.MX is a routine decision, since each is built to power a particular i.MX family with the rails and the sequencing that processor’s reference design expects.

The current each rail has to deliver is part of that map. A core rail on a busy SoC can pull several amps in bursts as the cores ramp, while a real-time clock rail draws only microamps, so a matched PMIC sizes each of its regulators to the rail it feeds and groups the high-current and the low-current rails the way the processor draws them and a general part has to be checked rail by rail against the processor’s demand. Getting one rail undersized shows up as a brownout only when that part of the chip wakes up, which is a fault that passes a quiet bench test and fails in the field.

The match is the whole point.

The match is what the whole selection comes down to. A PMIC with the wrong rail count or the wrong sequencing can power a processor only with external parts bolted on to fill the gaps, which gives back the integration the PMIC was chosen for. Picking the PMIC the processor’s reference design names, or one validated against it, is what keeps the power section from becoming a project of its own. The reference design carries more than the part number: the recommended inductor and capacitor values per rail, the sequencing settings, and the layout for the sensitive feedback nodes come with it, and following them is how a team inherits the vendor’s validation instead of repeating it.

The parts for each processor tier

For mid-range and application-grade processors, several vendors offer multi-rail parts. The MPS MP54 and MP58 multi-rail PMICs cover a band of FPGA and SoC designs that need several rails without a processor-specific part, and the integration of the ADI ADP5052 and ADP5054 packs several bucks and an LDO into one part for a dense board that does not need a sequencing engine tied to one SoC. These general parts give a configurable sequence and adjustable rails, so a team can fit them to a processor that has no dedicated PMIC at the cost of doing the matching work itself.

The China-designed SoCs bring their own power needs. A Rockchip design that goes past its reference uses the PMIC options for the RK3568 beyond the reference, since the chip ships with a recommended companion PMIC and a design that strays from it has to rebuild the rail map and the sequencing by hand. That work is doable, since the rail voltages and the order are published, but it moves the power tree from a copied, proven block to one the team owns and has to verify on its own bench.

An FPGA sits between the two cases. It needs many rails like a processor, with its own power-up order between the core, the auxiliary, and the I/O banks, yet it rarely has a single named companion PMIC the way an i.MX does, so a multi-rail part programmed for the FPGA’s sequence is the usual answer. The configuration is held in the PMIC and loaded at start-up, which lets one part serve several FPGA densities on the same board family.

A PMIC tied to one processor and a general multi-rail part solve different problems, since the matched part saves the sequencing work while the general part gives the freedom to power a chip no PMIC was built for.

The failure that hides in the power-up

The detail a PMIC exists to handle is sequencing, and getting it wrong is the failure that wastes the bring-up schedule fastest. How PMIC power sequencing causes boot failures comes down to rails arriving in the wrong order or at the wrong time, since a processor whose I/O powers before its core can latch up or fail to start, and the symptom is a board that sometimes boots and sometimes does not, the kind of intermittent fault that costs days to trace back to a few milliseconds of rail timing. A PMIC built for the processor brings the rails up in the order the silicon wants, which is the protection a hand-built supply of discrete regulators and a sequencer has to get right on its own. The hardest part of that is the timing between rails, since some processors want a few milliseconds of gap and others a defined slew on each rail, and a discrete design hits those numbers only with care that the matched PMIC has already taken.

Shutdown carries the same ordering in reverse. A processor that loses its core rail while its I/O is still driven can latch up on the way down as surely as on the way up, so the PMIC ramps the rails down in a controlled order on a power-off or a fault, and a brown-out on the input has to be caught and handled before the rails collapse at random. The down-sequence is part of what a matched PMIC is validated for.

Sequencing is set and read over a control bus, and the choice of bus shapes the design. Choosing between PMBus and I2C for a PMIC decides how the rails are configured, monitored, and turned on, since PMBus carries a defined command set for power telemetry while plain I2C leaves more to the part’s own registers. The bus is how the processor and the PMIC coordinate the start-up and watch the rails once they are live. It also carries the fault reporting, so a rail that droops or a regulator that overheats can raise a flag the processor reads, which turns a silent power problem into one the firmware can log and act on.

The heat the package has to carry

A PMIC concentrates several regulators in one package, so the heat from all of them lands in one place, and managing thermal management for QFN PMICs in production is the difference between a part that holds its rails and one that throttles or shuts down under load. The QFN package puts a thermal pad under the die, so the copper and the vias beneath it carry the heat into the board, and a layout that starves that pad runs the part hot. The power lost across several integrated rails adds up, and on a sealed enclosure with no airflow that total sets the thermal limit before any single rail’s current does. The efficiency of each integrated regulator decides how much of that heat there is, so a PMIC running its bucks in a high-efficiency mode at light load keeps both the runtime and the case temperature in range on a battery device.

The same package that saves the board space concentrates the heat, so the integration pays off only when the layout gives the PMIC enough copper to shed the heat it makes.

How PMICs get chosen and sourced

A PMIC is the hardest part on the board to substitute, since it is bound to the processor by its rail map and its sequencing, and no other part carries the same combination. A PMIC swapped for a near match can power the wrong rails or sequence them wrong, so a board that loses its specified PMIC mid-production faces a real redesign, since no near part drops straight in. A broad-line distributor that carries the PMIC families alongside the processors they pair with lets a design hold both in view, and tracks the long-term supply of a part the design cannot easily replace. The supply horizons of the two are read together, since a PMIC that goes end-of-life before its processor leaves a board with a working SoC and nothing matched to power it, a gap that forces a power redesign on an otherwise current design. The PMIC and the processor are sourced as a pair, since a processor in stock with no PMIC to power it is a board that cannot ship. A late substitution touches the firmware as well, since the PMIC’s register map and its sequence settings are written into the boot code, so changing the part means re-validating the power-up and not only the schematic. That coupling is the reason the PMIC is pinned down early and watched for supply as closely as the processor it serves.

The judgment that fits

Pick the PMIC the processor’s reference design names, or one validated against its rail map and its sequencing, give it the copper it needs to carry its heat, and confirm the control bus the rest of the board expects to talk to it on. The eight pages below take the matched parts and the design details one at a time, from the i.MX and TI companion PMICs through the sequencing, the control bus, and the thermal design that decide whether the rails come up clean.